The present disclosure relates to a precharge voltage supply circuit and a semiconductor device using the same, and more particularly to a precharge voltage supply circuit which is capable of, in a power down mode, reducing the amount of leakage current flowing through a bridge-formed region and supplying a precharge voltage of a proper level, so as to suppress generation of logically erroneous bits.
Recently, with a higher integration of semiconductor devices, each part of the semiconductor devices has been gradually reduced in occupied area thereof. Particularly, in a dynamic random access memory (DRAM) semiconductor device, the pitch of gates in the semiconductor device has been reduced, resulting in an increased possibility that a bridge will be formed between a word line and a bit line in a manufacturing process of the semiconductor device. The formation of the bridge between the word line and the bit line mainly results from gate residue, namely, polysilicon not completely removed after etching of a polysilicon film to form a gate, or undesirable removal of a nitride film on the gate during a chemical mechanical polishing (CMP) process, causing weakness of the corresponding region.
FIG. 1 is a sectional view illustrating the formation of a bridge between a word line and a bit line in a semiconductor device. As shown in FIG. 1, when a bridge is formed between a word line and a bit line, a current path is established between the word line and the bit line. As a result, charges in the bit line flow along the current path in a power down mode of the semiconductor device, resulting in generation of undesirable leakage current between the word line and the bit line in the power down mode. Of course, it may be possible to replace a failed cell, in which the bridge is formed, with a redundant cell. In this case, however, the failed cell still remains in the semiconductor device, so that leakage current still flows through the failed cell.
FIG. 2 is a graph illustrating the amount of leakage current generated due to failures in rows/columns caused by a bridge between a word line and a bit line. Referring to FIG. 2, it can be seen that the amount of leakage current is increased in proportion to the number of failed rows/columns caused by failed cells. The leakage current unnecessarily consumed per failed cell is about 9 μA, which corresponds to 7 to 10% of a limit value specified in Standard Specification for standby current in low-power semiconductor devices. The increase in leakage current caused by a bridge formed between a word line and a bit line adversely affects the current characteristics of the semiconductor device. Consequently, such a leakage current increase serves as a major factor degrading the throughput of the semiconductor device.
Of course, in order to reduce leakage current caused by failed cells in a semiconductor device, a method of adding a high resistance component to a precharge voltage supply circuit in the semiconductor device to achieve a reduction in leakage current may be conceived. However, although this method may reduce leakage current somewhat, there is a problem in that it is impossible to avoid logical errors which may occur due to various resistance components resulting from the formation of a bridge between a bit line and a word line.
In other words, a resistance component in a current path between a bit line and a word line, established due to the formation of a bridge between the bit line and the word line, has various values depending on various factors, such as the type of a semiconductor device and a position and frequency at which it is generated. Provided that the resistance value in the current path is very low, a voltage applied to the inside of a DRAM cell will become excessively low due to a high resistance component installed in the precharge voltage supply circuit, thus making it impossible to maintain a precharge voltage at a proper level, leading to generation of bits with logical errors.